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? 1998 microchip technology inc. preliminary ds21207b-page 1 m 93c66a/b features single supply 5.0v operation low power cmos technology - 1 ma active current (typical) -1 m a standby current (maximum) 512x 8 bit organization (93c66a) 256x 16 bit organization (93c66b) self-timed erase and write cycles (including auto-erase) automatic eral before wral power on/off data protection circuitry industry standard 3-wire serial interface device status signal during erase/write cycles sequential read function 100,000 e/w cycles guaranteed data retention > 200 years 8-pin pdip and soic packages available for the following temperature ranges: description the microchip technology inc. 93c66a/b is a 4k-bit, low-voltage serial electrically erasable prom. the device memory is con?ured as 512 x 8 bits (93c66a) or 256 x 16 bits (93c66b). advanced cmos technology makes this device ideal for low-power, nonvolatile memory applications. the 93c66a/b is available in standard 8-pin dip and surface mount soic packages. this device is only recommended for 5v automotive temperature applications. for all commercial and industrial temperature applica- tions, the 93lc66a/b is recommended. package type block diagram - automotive (e): -40 c to +125 c 93c66a/b cs clk di do 1 2 3 4 8 7 6 5 v cc nc nc v ss cs clk di do v cc nc nc v ss 93c66a/b soic 1 2 3 4 pdip 8 7 6 5 v cc v ss di cs clk do memory array address decoder address counter data register output buffer memory decode logic clock generator 4k 5.0v automotive temperature microwire serial eeprom microwire is a registered trademark of national semiconductor.
93c66a/b ds21207b-page 2 preliminary ? 1998 microchip technology inc. 1.0 electrical characteristics 1.1 maxim um ratings* v cc ...................................................................................7.0v all inputs and outputs w.r.t. v ss ................ -0.6v to v cc +1.0v storage temperature .....................................-65 c to +150 c ambient temp. with power applied.................-65 c to +125 c soldering temperature of leads (10 seconds) ............. +300 c esd protection on all pins................................................4 kv *notice: stresses above those listed under ?aximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this speci?ation is not implied. exposure to maximum rating conditions for extended peri- ods may affect device reliability. table 1-1: pin function table name function cs chip select clk serial data clock di serial data input do serial data output v ss ground nc no connect v cc power supply table 1-2: dc and ac electrical characteristics all parameters apply over the speci?d operating ranges unless otherwise noted automotive (e):v cc = +4.5v to +5.5vtamb = -40 c to +125 c parameter symbol min. max. units conditions high level input voltage v ih 2.0 v cc +1 v (note 2) low level input voltage v il -0.3 0.8 v low level output voltage v ol 0.4 v i ol = 2.1 ma; v cc = 4.5v high level output voltage v oh 2.4 v i oh = -400 m a; v cc = 4.5v input leakage current i li -10 10 m av in = v ss to v cc output leakage current i lo -10 10 m av out = v ss to v cc pin capacitance (all inputs/outputs) c in , c out ?pf v in /v out = 0 v (notes 1 & 2) tamb = +25 c, f clk = 1 mhz operating current i cc write 1.5 ma i cc read 1 ma standby current i ccs ? m a cs = v ss clock frequency f clk 2 mhz clock high time t ckh 250 ns clock low time t ckl 250 ns chip select setup time t css 50 ns relative to clk chip select hold time t csh 0 ns relative to clk chip select low time t csl 250 ns data input setup time t dis 100 ns relative to clk data input hold time t dih 100 ns relative to clk data output delay time t pd 400 ns c l = 100 pf data output disable time t cz 100 ns c l = 100 pf (note 2) status valid time t sv 500 ns c l = 100 pf program cycle time t wc 2 ms erase/write mode t ec 6 ms eral mode t wl 15 ms wral mode endurance 100k cycles 25 c, v cc = 5.0v, block mode (note 3) note 1: this parameter is tested at tamb = 25 c and f clk = 1 mhz. 2: this parameter is periodically sampled and not 100% tested. 3: this application is not tested but guaranteed by characterization. for endurance estimates in a speci? application, please consult the total endurance model which may be obtained on microchips bbs or web- site.
? 1998 microchip technology inc. preliminary ds21207b-page 3 93c66a/b 2.0 pin description 2.1 chip select (cs) a high level selects the device; a low level deselects the device and forces it into standby mode. however, a pro- gramming cycle which is already in progress will be completed, regardless of the chip select (cs) input signal. if cs is brought low during a program cycle, the device will go into standby mode as soon as the pro- gramming cycle is completed. cs must be low for 250 ns minimum (t csl ) between consecutive instructions. if cs is low, the internal con- trol logic is held in a reset status. 2.2 serial cloc k (clk) the serial clock (clk) is used to synchronize the com- munication between a master device and the 93c66a/b. opcodes, addresses, and data bits are clocked in on the positive edge of clk. data bits are also clocked out on the positive edge of clk. clk can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (t ckh ) and clock low time (t ckl ). this gives the controlling master freedom in preparing opcode, address, and data. clk is a ?on't care if cs is low (device deselected). if cs is high, but the start condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for a start condition). clk cycles are not required during the self-timed write (i.e., auto erase/write) cycle. after detecting a start condition, the speci?d num- ber of clock cycles (respectively low to high transitions of clk) must be provided. these clock cycles are required to clock in all required opcodes, addresses, and data bits before an instruction is executed (table 2-1 and table 2-2). clk and di then become don't care inputs waiting for a new start condition to be detected. 2.3 data in (di) data in (di) is used to clock in a start bit, opcode, address, and data synchronously with the clk input. 2.4 data out (do) data out (do) is used in the read mode to output data synchronously with the clk input (t pd after the positive edge of clk). this pin also provides ready/b usy status informa- tion during erase and write cycles. ready/b usy status information is available on the do pin if cs is brought high after being low for minimum chip select low time (t csl ) and an erase or write operation has been initiated. the status signal is not available on do, if cs is held low during the entire erase or write cycle. in this case, do is in the high-z mode. if status is checked after the erase/write cycle, the data line will be high to indicate the device is ready. table 2-1: instruction set for 93c66a table 2-2: instruction set for 93c66b note: cs must go low between consecutive instructions. instruction sb opcode address data in data out req. clk cycles erase 1 11 a8 a7 a6 a5 a4 a3 a2 a1 a0 (rdy/bsy )12 eral 1 00 1 0xxxxxxx (rd y/bsy )12 ewds 1 00 0 0xxxxxxx high-z 12 ewen 1 00 1 1xxxxxxx high-z 12 read 1 10 a8a7a6a5a4a3a2a1a0 d7 - d0 20 write 1 01 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 - d0 (rdy/bsy )20 wral 1 00 0 1xxxxxxx d7 - d0 (rd y/bsy )20 instruction sb opcode address data in data out req. clk cycles erase 1 11 a7 a6 a5 a4 a3 a2 a1 a0 (rdy/bsy )11 eral 1 00 1 0xxxxxx (rd y/bsy )11 ewen 1 00 1 1xxxxxx high-z 11 ewds 1 00 0 0xxxxxx high-z 11 read 1 10 a7 a6 a5 a4 a3 a2 a1 a0 d15 - d0 27 write 1 01 a7 a6 a5 a4 a3 a2 a1 a0 d15 - d0 (rdy/bsy )27 wral 1 00 0 1xxxxxx d15 - d0 (rdy/bsy )27
93c66a/b ds21207b-page 4 preliminary ? 1998 microchip technology inc. 3.0 functional description instructions, addresses, and write data are clocked into the di pin on the rising edge of the clock (clk). the do pin is normally held in a high-z state except when reading data from the device, or when checking the ready/b usy status during a programming operation. the ready/b usy status can be veri?d during an erase/write operation by polling the do pin; do low indicates that programming is still in progress, while do high indicates the device is ready. the do will enter the high-z state on the falling edge of the cs. 3.1 st ar t condition the start bit is detected by the device if cs and di are both high with respect to the positive edge of clk for the ?st time. before a start condition is detected, cs, clk, and di may change in any combination (except to that of a start condition), without resulting in any device oper- ation (erase, eral, ewds, ewen, read, write, and wral). as soon as cs is high, the device is no longer in the standby mode. an instruction following a start condition will only be executed if the required amount of opcodes, addresses, and data bits for any particular instruction is clocked in. after execution of an instruction (i.e., clock in or out of the last required address or data bit) clk and di become don't care bits until a new start condition is detected. 3.2 data in (di) and data out (do) it is possible to connect the data in (di) and data out (di) pins together. however, with this con?uration it is possible for a ?us con?ct to occur during the ?ummy zero that precedes the read operation, if a0 is a logic-high level. under such a condition the voltage level seen at do is unde?ed and will depend upon the relative impedances of do and the signal source driv- ing a0. the higher the current sourcing capability of a0, the higher the voltage at the do pin. 3.3 data pr otection during power-up, all programming modes of operation are inhibited until v cc has reached a level greater than 3.8v. during power-down, the source data protection circuitry acts to inhibit all programming modes when vcc has fallen below 3.8v at nominal conditions. the erase/write disable (ewds) and erase/ write enable (ewen) commands give additional pro- tection against accidentally programming during nor- mal operation. after power-up, the device is automatically in the ewds mode. therefore, an ewen instruction must be performed before any erase or write instruction can be executed. figure 3-1: synchronous data timing cs v ih v il v ih v il v ih v il v oh v ol v oh v ol clk di do (read) do (program) t css t dis t ckh t ckl t dih t pd t csh t pd t cz status valid t sv t cz note: ac test conditions: v il = 0.4v, v ih = 2.4v.
? 1998 microchip technology inc. preliminary ds21207b-page 5 93c66a/b 3.4 erase the erase instruction forces all data bits of the spec- i?d address to the logical ? state. this cycle begins on the rising clock edge of the last address bit. the do pin indicates the ready/b usy status of the device if cs is brought high after a minimum of 250 ns low (t csl ). do at logical ? indicates that program- ming is still in progress. do at logical ? indicates that the register at the speci?d address has been erased and the device is ready for another instruction. 3.5 erase all (eral) the erase all (eral) instruction will erase the entire memory array to the logical ? state. the eral cycle is identical to the erase cycle, except for the different opcode. the eral cycle is completely self-timed and commences at the rising clock edge of the last address bit. clocking of the clk pin is not necessary after the device has entered the eral cycle. the do pin indicates the ready/b usy status of the device, if cs is brought high after a minimum of 250 ns low (t csl ) and before the entire eral cycle is com- plete. figure 3-2: erase timing figure 3-3: eral timing cs clk di do t csl check status 1 1 1a n a n -1 a n -2 a0 t sv t cz busy ready high-z t wc high-z cs clk di do t csl check status 100 10x x t sv t cz busy ready high-z t ec high-z
93c66a/b ds21207b-page 6 preliminary ? 1998 microchip technology inc. 3.6 erase/write disab le and enab le (ewds/ewen) the device powers up in the erase/write disable (ewds) state. all programming modes must be pre- ceded by an erase/write enable (ewen) instruc- tion. once the ewen instruction is executed, programming remains enabled until an ewds instruc- tion is executed or v cc is removed from the device. to protect against accidental data disturbance, the ewds instruction can be used to disable all erase/write functions and should follow all programming opera- tions. execution of a read instruction is independent of both the ewen and ewds instructions. 3.7 read the read instruction outputs the serial data of the addressed memory location on the do pin. a dummy zero bit precedes the 8-bit (93c66a) or 16-bit (93c66b) output string. the output data bits will toggle on the rising edge of the clk and are stable after the speci?d time delay (t pd ). sequential read is possible when cs is held high. the memory data will automati- cally cycle to the next register and output sequentially. figure 3-4: ewds timing figure 3-5: ewen timing figure 3-6: read timing cs clk di 10 000x x t csl 1x cs clk di 00 1 1x t csl cs clk di do 110 an a0 high-z 0dx d0 dx d0 dx d0
? 1998 microchip technology inc. preliminary ds21207b-page 7 93c66a/b 3.8 write the write instruction is followed by 8 bits (93c66a) or 16 bits (93c66b) of data which are written into the speci?d address. after the last data bit is clocked into the di pin the self-timed auto-erase and programming cycle begins. the do pin indicates the ready/b usy status of the device, if cs is brought high after a minimum of 250 ns low (t csl ) and before the entire write cycle is complete. do at logical ? indicates that programming is still in progress. do at logical ? indicates that the register at the speci?d address has been written with the data speci?d and the device is ready for another instruc- tion. 3.9 write all (wral) the wral instruction will write the entire memory array with the data speci?d in the command. the wral cycle is completely self-timed and commences at the rising clock edge of the last data bit. clocking of the clk pin is not necessary after the device has entered the wral cycle. the wral command does include an automatic eral cycle for the device. there- fore, the wral instruction does not require an eral instruction but the chip must be in the ewen status. the do pin indicates the ready/b usy status of the device if cs is brought high after a minimum of 250 ns low (t csl ). figure 3-7: write timing figure 3-8: wral timing cs clk di do 1 0 1 an a0 dx d0 b usy ready high-z high-z tw c t csl t cz t sv cs clk di do high-z 1 0 0 01 x x dx d0 high-z b usy ready t wl t csl t sv t cz
93c66a/b ds21207b-page 8 preliminary ? 1998 microchip technology inc. notes:
? 1998 microchip technology inc. preliminary ds21207b-page 9 93c66a/b notes:
93c66a/b ds21207b-page 10 preliminary ? 1998 microchip technology inc. notes:
? 1998 microchip technology inc. preliminary ds21207b-page 11 93c66a/b 93c66a/b product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales of?e. sales and suppor t package: p = plastic dip (300 mil body), 8-lead sn = plastic soic (150 mil body), 8-lead temperature range: e = -40 c to +125 c device: 93c66a 4k microwire serial eeprom (x8) 93c66at 4k microwire serial eeprom (x8) tape and reel 93c66b 4k microwire serial eeprom (x16) 93c66bt 4k microwire serial eeprom (x16) tape and reel 93c66a/b /p data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales of?e. 2. the microchip corporate literature center u.s. fax: (602) 786-7277. 3. the microchips bulletin board, via your local compuserve number (compuserve membership not required).
information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip t echnology incorporated with respect to the accuracy or use of such information, or infringe m ent of patents or other intellectual property rights arising from such use or othe r wise. use of microchip s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or othe r wise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip t echnolog y inc. in the u.s.a. and other countries. all rights rese r ved. all other trademarks mentioned herein are the property of their respective companies. ds2120 7 b-page 12 preliminary ? 1998 microchip technology inc. all r ights rese r v ed . ? 1998, microchi p t echnology inco r porated, usa . 1/98 p r inted on recycled pape r . m americas corporate of?e microchip t echnolog y inc. 235 5 w est chandler blvd. chandle r , az 85224-6199 t el : 602-786-7200 f ax : 602-786-7277 technical support: 602 786-7627 web: http://ww w .microchi p .com atlanta microchip t echnolog y inc. 500 sugar mill road, suite 200b atlanta, ga 30350 t el : 770-640-0034 f ax : 770-640-0307 boston microchip t echnolog y inc. 5 mount r o y al a v enue ma r lborough, ma 01752 t el : 508-480-9990 f ax : 508-480-8575 chicago microchip t echnolog y inc. 333 pierce road, suite 180 itasca, il 60143 t el : 630-285-0071 f ax : 630-285-0075 dallas microchip t echnolog y inc. 14651 dallas p a r k w a y , suite 816 dalla s , tx 75240-8809 t el : 972-991-7177 f ax : 972-991-8588 d a yton microchip t echnolog y inc. t wo prestige plac e , suite 150 miamis b urg, oh 45342 t el : 937-291-1654 f ax : 937-291-9175 los angeles microchip t echnolog y inc. 1820 1 v on ka r man, suite 1090 i r vin e , ca 92612 t el : 714-263-1888 f ax : 714-263-1338 n e w y ork microchip t echnolog y inc. 150 motor p a r k w a y , suite 202 hauppaug e , ny 11788 t el : 516-273-5305 f ax : 516-273-5335 san jose microchip t echnolog y inc. 2107 no r th first street, suite 590 san jos e , ca 95131 t el : 408-436-7950 f ax : 408-436-7955 t o r onto microchip t echnolog y inc. 5925 ai r po r t road, suite 200 mississauga, onta r io l4v 1w1, canada t el : 905-405-6279 f ax : 905-405-6253 asia/ p a cific hong k ong microchip asia p aci? r m 3801 b , t o wer t wo metroplaza 223 hing f ong road k w ai f ong, n. t ., hong k ong t el : 852-2-401-1200 f ax : 852-2-401-3431 india microchip t echnolog y inc. india liaison of?e n o . 6, legac y , co n v ent road bangalore 560 025, india t el : 91-80-229-0061 f ax : 91-80-229-0062 k orea microchip t echnolog y k orea 168-1 , y oungbo bldg . 3 floor samsung-dong, kangnam- k u seoul, k orea t el : 82-2-554-7200 f ax : 82-2-558-5934 shanghai microchip t echnology rm 406 shanghai golden b r idge bldg. 207 7 y an?n roa d w est, hong qiao dist r ict shanghai, prc 200335 t el : 86-21-6275-5700 f ax : 86 21-6275-5060 singapore microchip t echnology t ai w an singapore branch 200 middle road #07-02 p r ime centre singapore 188980 t el : 65-334-8870 f ax : 65-334-8850 t aiwan , r. o .c microchip t echnology t ai w an 10f-1c 207 t ung hua no r th road t aipei, t ai w an , r o c t el : 886-2-2717-7175 f ax : 886-2-2545-0139 eu r ope united kingdom a r i z ona microchi p t echnology ltd. 505 eskdale road winnersh t r iangle w okingham be r kshir e , england rg41 5tu t el : 44-1189-21-585 8 f ax : 44-1189-21-5835 france a r i z ona microchi p t echnology sarl zone indust r ielle de la bonde 2 rue du buisson aux f raises 91300 mass y , f rance t el : 33-1-69-53-63-20 f ax : 33-1-69-30-90-79 germa n y a r i z ona microchi p t echnology gmbh gust a v-heinemann-ring 125 d-81739 m?chen, ge r ma n y t el : 49-89-627-144 0 f ax : 49-89-627-144-44 ita l y a r i z ona microchi p t echnology srl centro direzionale colleoni p alaz z o t au r us 1 v . le colleoni 1 20041 agrate b r ianza milan, italy t el : 39-39-6899939 f ax : 39-39-6899883 j a p a n microchi p t echnology intl . inc. ben e x s-1 6f 3-18-20, shi n y o k ohama k ohoku- k u, y o k ohama-shi kanag a w a 222 j apan t el : 81-45-471- 6166 f ax : 81-45-471-6122 12/30/97 w orldwide s ales and s ervice

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